Strategy and Synergy for Security
Strategy and Synergy for Security
Strategy and Synergy for Security
SETS, MGR Knowledge City, Taramani, Chennai-600113
Strategy and Synergy for Security

Society for Electronic Transactions and Security

(Under O/o The Principal Scientific Adviser to the Govt. of India )

MGR Knowledge City, Taramani, Chennai - 600113

Society for Electronic Transactions and Security


(Under O/o The Principal Scientific Adviser to the Govt. of India )

MGR Knowledge City, Taramani, Chennai - 600113

Society for Electronic Transactions and Security


(Under O/o The Principal Scientific Adviser to the Govt. of India)

MGR Knowledge City, Taramani, Chennai - 600113



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SETS
  • Home
  • About Us
    • History
    • SETS & Its Charter
    • Messages from the Former Presidents
    • Message from the Former Executive Director
  • Organizational Profile
    • ED'S Profile
    • Society Members
    • Governing Council Members
    • Advisory Board
    • Organization Chart
  • R&D Activities
    • Journey of SETS
    • Cryptology & Computing Research
    • Hardware Security Research
    • Network Security Research
    • Quantum Security Research
  • Events
  • Achievements
  • Gallery
  • Careers
  • Infrastructure
  • Tenders
    • SETS Tenders
    • Expression of Interest (EoI)
  • Training & Services
    • Consultancy
    • Training
    • Short-Term R & D Excercises
    • Funded Projects
    • Request For Collaboration
  • Publications
  • Contact Us
  • Search
SETS
  • Home
  • About Us
    • History
    • SETS & Its Charter
    • Messages from the Former Presidents
    • Message from the Former Executive Director
  • Organization Profile
    • ED'S Profile
    • Society Members
    • Governing Council Members
    • Advisory Board
    • Organization Chart
  • R&D Activities
    • Journey of SETS
    • Cryptology & Computing Research
    • Hardware Security Research
    • Network Security Research
    • Quantum Security Research
  • Events
  • Achievements
  • Gallery
  • Careers
  • Infrastructure
  • Tenders
    • SETS Tenders
    • Expression of Interest (EoI)
  • Training & Services
    • Consultancy
    • Training
    • Short-Term R & D Excercises
    • Funded Projects
    • Request For Collaboration
  • Publications
  • Contact Us
  • Search

Hardware Security Research

    SETS has rich expertise in the area of Hardware Security. Hardware Security includes assurance of root of trust, trusted execution environment and development of cryptographic hardware. Research in cryptographic hardware (devices that execute cryptography algorithms) becomes essential as vulnerabilities in cryptographic hardware can compromise the security of the entire infrastructure. In order to address the raising concerns, SETS has set evaluation of cryptographic algorithms, development of secure hardware implementations of cryptosystems as its prime areas of focus under Hardware Security Research.

    Current Activities

    Side-channel analysis (SCA) is demonstrated to be an effective way to recover secret keys stored in cryptographic ICs by observing and recording its power consumption. SETS is capable of performing vulnerability analysis of symmetric (such as stream and block ciphers and authenticated encryption schemes), asymmetric key ciphers (RSA, DSA, ECC) and post quantum crypto algorithms, against SCA attack and development of countermeasures to protect the cryptographic implementation.

    Utilisation of generic SCA countermeasures would benefit critical sectors. SETS is exploring the security properties of generic countermeasures that protect the cryptographic module.

    SETS is establishing a hardware test lab infrastructure to evaluate the software exploitable hardware vulnerabilities

    SETS has expertise in examining implementation mechanisms of PUF and design practices to achieve scalable, efficient and secure PUF-based cryptographic schemes. In addition, SETS has developed True Random Number Generator (TRNG) using PUF and developed a tool to test the performance of TRNG.


    Research Collaborations

    SETS has collaborated with National level organisations to work on the analysis of their crypto modules against Side Channel Attacks and development of FIPS-140-2 compliant crypto modules for indigenous HSM. SETS has ongoing engagement with IIT-Bombay, IIT-Delhi and SCL-Chandigarh in the development of PUF based technologies of national importance.


    Side Channel Analysis Lab

    SETS has established differential power and Electro-Magnetic measurement and analysis set-up on Field Programmable Gate Array (FPGA) and micro-controller to conduct side channel analysis. Using the set-up, various types of crypto modules have been evaluated and appropriate countermeasures have also been developed



Hardware Security Research

    SETS has rich expertise in the area of Hardware Security. Hardware Security includes assurance of root of trust, trusted execution environment and development of cryptographic hardware. Research in cryptographic hardware (devices that execute cryptography algorithms) becomes essential as vulnerabilities in cryptographic hardware can compromise the security of the entire infrastructure. In order to address the raising concerns, SETS has set evaluation of cryptographic algorithms, development of secure hardware implementations of cryptosystems as its prime areas of focus under Hardware Security Research.

    Current Activities

    Side-channel analysis (SCA) is demonstrated to be an effective way to recover secret keys stored in cryptographic ICs by observing and recording its power consumption. SETS is capable of performing vulnerability analysis of symmetric (such as stream and block ciphers and authenticated encryption schemes), asymmetric key ciphers (RSA, DSA, ECC) and post quantum crypto algorithms, against SCA attack and development of countermeasures to protect the cryptographic implementation.

    Utilisation of generic SCA countermeasures would benefit critical sectors. SETS is exploring the security properties of generic countermeasures that protect the cryptographic module.

    SETS is establishing a hardware test lab infrastructure to evaluate the software exploitable hardware vulnerabilities

    SETS has expertise in examining implementation mechanisms of PUF and design practices to achieve scalable, efficient and secure PUF-based cryptographic schemes. In addition, SETS has developed True Random Number Generator (TRNG) using PUF and developed a tool to test the performance of TRNG.


    Research Collaborations

    SETS has collaborated with National level organisations to work on the analysis of their crypto modules against Side Channel Attacks and development of FIPS-140-2 compliant crypto modules for indigenous HSM. SETS has ongoing engagement with IIT-Bombay, IIT-Delhi and SCL-Chandigarh in the development of PUF based technologies of national importance.


    Side Channel Analysis Lab

    SETS has established differential power and Electro-Magnetic measurement and analysis set-up on Field Programmable Gate Array (FPGA) and micro-controller to conduct side channel analysis. Using the set-up, various types of crypto modules have been evaluated and appropriate countermeasures have also been developed



Copyright 2018 © SETS | ALL Rights Reserved | Last Updated: Friday, 22-Feb, 2019.

Copyright 2018 © SETS | ALL Rights Reserved