Scientist
Over nine years of R&D expereince in various Government Institutions like C-DAC, Indian Telephone Industries (ITI) Ltd and Society for Electronic Transactions and Security (SETS).
Working as the Co-PI in the “Establishment of hardware testing facility to detect hardware trojan phase-I” project and completed the Analysis, design and development of SCA-resistant crypto module for hardware security module for CRL-BEL as Co-PI at SETS.
Worked @VVDN Technologies, Cochin (2019-20) for the Implementation of LDPC and Polar Encoding/ Decoding modules in the uplink and downlink physical layers for 5G NR
Worked @R&D ITI Ltd. Bangalore (2015-19) for the design and implementation of IP based crypto products and crypto algorithms in FPGA; for Grade 4 as per CPC and SAG requirements; for the 10/100 Mbps, 1Gbps and 10 Gbps IP based crypto products; with Layer 2, Layer 3, Layer 4 and Tunnel modes of encryption; in Xilinx and Intel FPGAs for defence customers
Worked @C-DAC Thiruvananthapuram (2013-14) for the Implementation of FPGA based 8051-microcontroller using VHDL for the project of developing smart cards for Government of India
Educational qualifications are M. Tech in VLSI & Embedded Systems from CUSAT in 2013; MBA in Marketing from Pondicherry University in 2021 and B.Tech in Electronics and Communication from University of Calicut in 2011
Areas of interest include Security analysis of COTS devices, Analysis of Wireless Protocols, Secure Drone communication and Counter UAS technologies, RTL design and implementation of crypto algorithms, Cryptography and Cryptanalysis.
