Society for Electronic Transactions and Security(SETS)

(Under O/o The Principal Scientific Adviser to the Govt. of India )

MGR Knowledge City, CIT Campus, Taramani, Chennai - 600113

Society for Electronic Transactions and Security

Workshop on Secure Processor 2026

SETS & C-DAC Jointly Offer Workshop on

SECURE PROCESSOR 2026

Date & Time: March 2nd – 3rd, 2026, 9:30 AM – 6:00 PM

Location: SETS, MGR Film City Road, CIT Campus, Taramani, Chennai, Tamil Nadu 600113

Mode of Attendance: OFFLINE

Workshop Overview

This workshop offers a forward-looking introduction to security considerations in modern processor design. It explores how trust is established at hardware level and how architectural choices influence long‑term system security.

Participants will explore evolving threat landscapes, including physical, side‑channel, and supply‑chain attacks, alongside future‑ready defensive design strategies.

Highlights of the Workshop

  • ✔️Architecture Fundamentals: Security-conscious processor design based on core computer architecture principles.
  • ✔️Hardware Root of Trust: On-chip identity, secure key storage, and reliable entropy generation.
  • ✔️Cryptographic Integration: PUF- and TRNG-based hardware mechanisms for unique device identity.
  • ✔️Lightweight Secure Boot: Efficient chain-of-trust boot for resource-constrained systems using cryptographic primitives.
  • ✔️Secure Boot Standards: Secure boot aligned with NIST SP 800-193 and PSA concepts.
  • ✔️Remote Attestation: Cryptographic proof of firmware integrity to a remote verifier.
  • ✔️Advanced Defense Mechanisms: Protection against side-channel attacks and physical tampering.
  • ✔️Trusted Execution: Secure isolation using Trusted Execution Environments (TEEs).
  • ✔️Open Architectures (RISC-V): Security opportunities, risks, and trade-offs in open architectures.
  • ✔️Hands-on Demos: Live root of trust & secure boot demonstrations.

Domain Experts

  1. Prof. Santanu Sarkar, IIT Madras
  2. Prof. Chester Rebeiro, IIT Madras
  3. Prof. Debapriya Basu Roy, IIT Kanpur
  4. Prof. Debayan Das, IISc Bengaluru
  5. Mr Libin, C-DAC Trivandrum
  6. Ms Sajna, C-DAC Trivandrum
  7. Ms Jaya, C-DAC Trivandrum
  8. Dr Natarajan, SETS Chennai
  9. Dr Tapabrata Roy, SETS Chennai
  10. Dr Vishal Saraswat, Bosch Global Software Technologies Pvt. Ltd.
  11. Mr Madhusudan, InCore Semiconductor Pvt. Ltd.

Registration

Fee: Free of Cost

Capacity: 40 Slots (First Come, First Serve)

Registration Link: https://forms.gle/CQpSJ9npoU3AnkcQ7

Target Audience: Scholars, Researchers, Academia, and Industry professionals.

Program Coordinators

  • Dr Prem Laxman Das, Scientist, SETS, Chennai.
  • Dr Natarajan, Scientist, SETS, Chennai.

Contact Information

For any queries or requests, kindly send an email to: qsrg_riscv@setsindia.net

📞 Mr Raja Adhithan: +91 73391 98134
📞 Mr Sheik Abdullah: +91 97153 10341

Event Schedule – Day 1

Date: 02/03/2026

Time Session Speaker
9:30 – 10:30 AM Inauguration  
10:30 – 11:00 AM Tea  
11:00 – 12:00 PM Secure processor and its industrial application Dr Vishal Saraswat
12:00 – 1:00 PM Lightweight Cryptography Dr Tapabrata Roy
1:00 – 2:00 PM Lunch  
2:00 – 3:00 PM Overview of a secure processor and its application Prof. Chester Rebeiro
3:00 – 4:00 PM Overview of Vega Processor and its application Mr Libin & Ms Sajna
4:00 – 4:30 PM Tea  
4:30 – 5:30 PM TBD Ms Jaya
5:30 – 6:00 PM C-DAC Demo  

Event Schedule – Day 2

Date: 03/03/2026

Time Session Speaker
9:30 – 10:30 AM TBD Prof. Debapriya Basu Roy
10:30 – 10:50 AM Tea  
10:50 – 11:50 AM Hard Problems in Cryptography: From Factorization to Post-Quantum Prof. Santanu Sarkar
11:50 – 12:50 PM SCA-resilient PQ-secure processor design Prof. Debayan Das
12:50 – 1:40 PM Lunch  
1:40 – 2:40 PM TBD Mr Madhusudan
2:40 – 3:40 PM Remote Attestation Dr Natarajan
3:40 – 4:00 PM Tea  
4:00 – 4:45 PM PUF & TRNG for Secure processor Mr Raja Adhithan
4:45 – 5:30 PM Secure Boot and its Standards Mr Sheik Abdullah
5:30 – 6:00 PM SETS Demo