Mrs. Gayathri G P joined SETS Chennai as Scientist C in the Quantum Security Research Group. She holds a Master’s degree in VLSI and Embedded Systems, with core expertise in microarchitecture, RTL design, and FPGA validation.
Prior to SETS, she worked at C-DAC Trivandrum on the MeitY-funded DIR-V initiative, contributing significantly to the design and development of India’s first indigenous microprocessor series VEGA and its supporting ecosystem. Her core contributions include the design, development and validation of IEEE 754-compliant floating-point coprocessors, memory controllers, peripheral IP cores, and the integration of hardware-level security features such as secure boot into VEGA-based System-on-Chip (SoC) architectures.
